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Medical Design verification engineer
Job Title: Design verification engineer
Location: US-CA-Menlo Park
Responsibilities:
- Write and augment existing test plans.
- Implement testbench and scoreboards / checkers.
- Implement test sequences as per plan and debug failures
- Achieve 100% functional and code coverage
- Work closely with designers, micro architects & f/w to resolve issues
- Ability to communicate & articulate clearly progress / issues with project leads
Skills:
- Atleast 2years exp in Medical industry.
- 5+ years of proven experience as a DV engineer
- Hands on experience with SV and UVM
- Hands on Experience with executable test plans and Coverage Driven verification
- Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
- Familiarity with C/C++
Preferred Qualifications:
- Python (or similar) scripting language
- ASIC design experience
- Experience in DSP based Audio or Computer Graphics or Compression is desirable
Required Skills:
Articulate, Engineer, Test Plans, Application-Specific Integrated Circuit, ASIC
Additional Skills:
ASIC Design, C++, Cadence, Debug, Python, Scripting, Synopsys
Please send CVs to vijaya@fusionlifesolutions.com